With this book learn how to:
make chip design easier
improve your design productivity
design efficient synthesizable models
write good HDL test harnesses
acquire good design and modeling pratices
This is an excellent reference book of common Verilog & VHDL design examples for RTL designers of all skills and experience levels. Along with Palnitkar and Bhasker's books on Verilog and synthesis, I have a copy of this book at both work and home.
About the only drawback is the very flimsy binding, totally unsuitable for a book intended as a reference. For whatever reason, the book has not been reprinted for many years. I am so concerned about not being able to replace them that I handle mine very carefully, as if they were Gutenberg Bibles. If you are involved in front-end ASIC/FPGA design, make sure you get one while it is still available - because you sure are not borrowing mine.