Designing cost-effective secure processors for embedded systems: Principles, challenges, and architectural solutions.

by Austin Rogers

Computer security in embedded systems is becoming more and more important as these systems diversify and proliferate, with the cost of security violations ranging from loss of revenue to loss of life. This dissertation addresses the problem of computer security at the hardware level, proposing a sign-and-verify secure processor architecture to ensure integrity (preventing the execution or use of unauthorized instructions or data) and confidentiality (preventing the unauthorized copying of instructions or data). Integrity is ensured by signing blocks of instructions or data when they are created and then verifying them when they are used. Confidentiality is ensured by encryption. We thoroughly explore the design challenges of the secure processor architecture, including signature generation, signature placement, code and data encryption, verification latency reduction, and memory overhead reduction. We propose a number of architectural solutions to address these challenges. A cycle-accurate simulator is used to explore the secure processor design space and evaluate the proposed solutions. We also develop a prototype secure processor in actual hardware, implemented on an FPGA-based platform. Our simulation results show that the proposed solutions can ensure security without incurring prohibitive performance overhead, and our hardware implementation demonstrates that our architecture is feasible and practical.

227 pages, Nook