Formal Verification: An Essential Toolkit for Modern VLSI Design by Erik Seligman

by Erik Seligman

"Formal An Essential Toolkit for Modern VLSI Design" presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. This can reduce time spent validating designs and more quickly reach a final design for manufacturing. Building on a basic knowledge of SystemVerilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. After reading this book, readers will be prepared to introduce FV in their organization and effectively deploy FV techniques to increase design and validation productivity. Learn formal verification algorithms to gain full coverage without exhaustive simulationUnderstand formal verification tools and how they differ from simulation toolsCreate instant test benches to gain insight into how models work and find initial bugsLearn from Intel insiders sharing their hard-won knowledge and solutions to complex design problems

Unknown Binding

First published August 31, 2015

Reviews

[Canberk · Rating 5 out of 5]

Geniunely one of the more fun technical books that I've read. Easy to digest with good learnings from real world scenarios.