Is your memory hierarchy stopping your microprocessor from performing at the high level it should be? Memory Cache, DRAM, Disk shows you how to resolve this problem. The book tells you everything you need to know about the logical design and operation, physical design and operation, performance characteristics and resulting design trade-offs, and the energy consumption of modern memory hierarchies. You learn how to to tackle the challenging optimization problems that result from the side-effects that can appear at any point in the entire hierarchy.As a result you will be able to design and emulate the entire memory hierarchy.
At 982 pages, this is the most-comprehensive book on memory systems I have seen. The 34-page list of references and the 28-page, 3-column index are testaments to the wide range of topics covered.
The book begins with a 54-page overview, followed by 31 chapters, organized in 4 parts.
Part I, Cache (6 chapters): Logical organization, content management, case studies.
Part II, DRAM (9 chapters): Details of signaling, timing, access protocols, controllers.
Part III, Disk (11 chapters): Physical & data layers, interfaces, performance, case studies.
Part IV, Cross-Cutting Issues (5 chapters): Physical & data layers, interfaces, performance.
Given that the book’s contents were compiled some two decades ago, it does not include discussions of flash memory or solid-state secondary storage. A 2026 book by Yu Hua, Big Memory Systems, which I have not yet examined, fills the recency void and has a focus on scaling issues, which are important considerations in the age of big data and AI.