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Coordinating Parallel Processors: A Partial Unification
Coordinating Parallel A Partial Unification presents a practical look at how shared memory and coordination primitives enable many processors to work together efficiently.
It explains a simple extension of the fetch-and-add idea and how it can empower a wide range of operations on network-based multiprocessors.
The text walks through hardware concepts from the NYU Ultracomputer, including processing elements, memory interfaces, and switch architectures. It shows how concurrent operations on a common memory cell can be executed with consistent, predictable timing, even as the number of processors scales up. The discussion connects theory to concrete design choices and how they support reliable synchronization.
Definitions and behavior of coordination primitives such as fetch-and-add, test-and-set, and swap. How a fetch-and-add switch handles multiple concurrent requests and preserves correctness. Generalization to fetch-and-(J) switches for any associative operation and implications for network design. Practical implementation notes for using these primitives to implement load and store operations. Ideal for readers of computer architecture and parallel processing who want a clear, example-driven view of coordinating large numbers of processors.
It explains a simple extension of the fetch-and-add idea and how it can empower a wide range of operations on network-based multiprocessors.
The text walks through hardware concepts from the NYU Ultracomputer, including processing elements, memory interfaces, and switch architectures. It shows how concurrent operations on a common memory cell can be executed with consistent, predictable timing, even as the number of processors scales up. The discussion connects theory to concrete design choices and how they support reliable synchronization.
Definitions and behavior of coordination primitives such as fetch-and-add, test-and-set, and swap. How a fetch-and-add switch handles multiple concurrent requests and preserves correctness. Generalization to fetch-and-(J) switches for any associative operation and implications for network design. Practical implementation notes for using these primitives to implement load and store operations. Ideal for readers of computer architecture and parallel processing who want a clear, example-driven view of coordinating large numbers of processors.
12 pages, Paperback
Published August 24, 2018
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