Logic Design and Verification Using Systemverilog

by Donald Serrell Thomas

SystemVerilog is a Hardware Description Language that enables designers to work at the higher levels of logic design abstractions that match the increased complexity of current day integrated circuit and field-programmable gate array (FPGA) designs. The majority of the book assumes a basic background in logic design and software programming concepts. It is directed • students currently in an introductory logic design course that also teaches SystemVerilog, • designers who want to update their skills from Verilog or VHDL, and • students in VLSI design and advanced logic design courses that include verification as well as design topics. The book starts with a tutorial introduction on hardware description languages and simulation. It proceeds to the register-transfer design topics of combinational and finite state machine (FSM) design — these mirror the topics of introductory logic design courses. The book covers the design of FSM-datapath designs and their interfaces, including SystemVerilog interfaces. Then it covers the more advanced topics of writing testbenches including using assertions and functional coverage. A comprehensive index provides easy access to the book’s topics.The goal of the book is to introduce the broad spectrum of features in the language in a way that complements introductory and advanced logic design and verification courses, and then provides a basis for further learning.

328 pages, Paperback

First published June 10, 2014

About the author

aka Francis Selwyn

Donald Serrell Thomas is an English author of (primarily) Victorian-era historical, crime and detective fiction, as well as books on factual crime and criminals, in particular several academic books on the history of crime in London. He has written a number of biographies, two volumes of poetry, and has also edited volumes of poetry by John Dryden and the Pre-Raphaelites.