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The RISC-V Reader: An Open Architecture Atlas
This Beta Edition of The RISC-V Reader was retired 11/9/17, as the First Edition is now available
- GenresProgrammingComputers
200 pages, Paperback
Published September 10, 2017
9 people are currently reading
79 people want to read
About the author
David Patterson
241 books8 followersLibrarian Note: There is more than one author by this name in the Goodreads database.
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Displaying 1 - 10 of 10 reviews
July 10, 2021
An excellent relatively short read. Reminds me of the CPU ISA version of K&R (aka The C Programming Language, by Kernighan & Ritchie). In a world of convoluted technology, the way RISC-V is presented is refreshing. Simple, clearly cutting out decades of cruft and design oversights from lessons learned from previous CPU ISAs, both disastrous and somewhat successful.
One of the few texts I've read in my lifetime which makes me somewhat optimistic about the future. Rather than using the conceit of ScFi and Ray Bradbury's The Toynbee Convector, RISC-V is rooted in prior research and academia, building upon decades of understandings cultivated from previous RISC CPU designs and improving upon them. If we are still dragging along the 1970s x86 CPU ISA as AMD64 or 1980s ARM CPU ISA further into the future, it will be far bleaker than the present. As it is, at least we had the MC6800, MOS6502, MC68000, MIPS and such decent CPU ISAs in the past, but the popularity and market share of the lowest common denominator of inefficient, baroque and needlessly complex licensed CPU ISAs instead means that RISC-V isn't merely a better, more efficient CPU ISA, given that it is open and freely licensed, it represents a cultural shift.
Rather than paying needless profits to entrenched industry "too big to fail" hegemonic peddlers, RISC-V is closer to what is enjoyed already in BSDs and Linux and other libre/free open source software projects: it's less about any specific vendor, and more about clean code, energy efficiency, reducing bugs which lead to the all too common phenomenon of security errors, providing useful features, jettisoning bad ideas from the past and collaboration with academics and independent researchers alike. RISC-V doesn't even implement an FPU, but if you've kept abreast of researchers exploring posit/unum alternatives to IEEE 754 floating point systems, that seems as if it is a design win, rather than perpetuating a legacy system due for replacement by better science.
Or, we could keep doing the same old thing that hasn't been working well enough, in which instance, you can ignore this book and the growing movement behind it.
If you want to be a real techno-luddite, maybe buy some Itanium systems if you really want to get fatalistic and continue ignoring RISC-V pandering FUD about how Intel, AMD, ARM or NVidia will be creating a future worth having, given all the problems already demonstrated by them in the past and present presenting more than enough evidence that they don't lead R&D in the field, so much as they capitalize upon it.
There are worse books on RISC-V, I would recommend avoiding Patrick H. Stakem's entirely. However, this one? It would be difficult to improve upon it in a meaningful way.
One of the few texts I've read in my lifetime which makes me somewhat optimistic about the future. Rather than using the conceit of ScFi and Ray Bradbury's The Toynbee Convector, RISC-V is rooted in prior research and academia, building upon decades of understandings cultivated from previous RISC CPU designs and improving upon them. If we are still dragging along the 1970s x86 CPU ISA as AMD64 or 1980s ARM CPU ISA further into the future, it will be far bleaker than the present. As it is, at least we had the MC6800, MOS6502, MC68000, MIPS and such decent CPU ISAs in the past, but the popularity and market share of the lowest common denominator of inefficient, baroque and needlessly complex licensed CPU ISAs instead means that RISC-V isn't merely a better, more efficient CPU ISA, given that it is open and freely licensed, it represents a cultural shift.
Rather than paying needless profits to entrenched industry "too big to fail" hegemonic peddlers, RISC-V is closer to what is enjoyed already in BSDs and Linux and other libre/free open source software projects: it's less about any specific vendor, and more about clean code, energy efficiency, reducing bugs which lead to the all too common phenomenon of security errors, providing useful features, jettisoning bad ideas from the past and collaboration with academics and independent researchers alike. RISC-V doesn't even implement an FPU, but if you've kept abreast of researchers exploring posit/unum alternatives to IEEE 754 floating point systems, that seems as if it is a design win, rather than perpetuating a legacy system due for replacement by better science.
Or, we could keep doing the same old thing that hasn't been working well enough, in which instance, you can ignore this book and the growing movement behind it.
If you want to be a real techno-luddite, maybe buy some Itanium systems if you really want to get fatalistic and continue ignoring RISC-V pandering FUD about how Intel, AMD, ARM or NVidia will be creating a future worth having, given all the problems already demonstrated by them in the past and present presenting more than enough evidence that they don't lead R&D in the field, so much as they capitalize upon it.
There are worse books on RISC-V, I would recommend avoiding Patrick H. Stakem's entirely. However, this one? It would be difficult to improve upon it in a meaningful way.
January 2, 2022
Good overview and reference for RISC V ISA but it could be more in depth. The author highlights the advantages over older architectures and the design decisions over specific features but never goes in detail. I believe it should be paired with "Computer Organization and Design RISC-V Edition: The Hardware Software Interface", which I haven't read yet, if you want a more in depth look of how a RISC-V was architected.
May 9, 2022
A great introduction to Risc-V explaining the instruction set and some background to the design decisions. As the introduction highlights it is a short book as the instruction set is simple to understand due to its clean layout.
Knocking off 1 star as the comparisons against other architectures is outdated and biased towards Risc-V. I.e. it compares Risc-V to an Arm A9 which was released in 2007. Hardly a fair comparison selecting a really old Arm CPU to compare against.
Knocking off 1 star as the comparisons against other architectures is outdated and biased towards Risc-V. I.e. it compares Risc-V to an Arm A9 which was released in 2007. Hardly a fair comparison selecting a really old Arm CPU to compare against.
June 24, 2024
A short book that gives a good overview of the RISC-V ISA. It includes a few programs that showcase the RV32I and RV64I instructions.
My favorite chapters were the one on the RV32V extension (but with a few more code examples would have been even better), and the one about the RISC-V privileged specification.
Some examples are implemented in x86_64, ARM64 and RISC-V assembly, so the implementations can be compared to one another.
My favorite chapters were the one on the RV32V extension (but with a few more code examples would have been even better), and the one about the RISC-V privileged specification.
Some examples are implemented in x86_64, ARM64 and RISC-V assembly, so the implementations can be compared to one another.
September 19, 2019
I had a quick skim through this book and bought it as a reference. I find it a quite succinct and useful description of RISC-V.
November 15, 2019
Emphasises how small the RISC-V instruction set is by the length of this short book, but I wish he had given more fuller descriptions.
July 18, 2021
Very interesting. And easy to understand.
April 10, 2023
Great book, very interesting, but the edition (and the printing) could be better.
December 20, 2024
god i wanna die
February 1, 2025
The book claims to be aimed at assembly language developers who already know at least one other architecture. That isn't really me. I did the usual m68k course in university 20 years ago and have mostly been working in much higher-level languages ever since. I don't really have any intention of developing software for risc-v.
I picked this up because I wanted to refresh myself on machine-language-level concepts, on a modern architecture, and risc-v seemed like it would be much more approachable than intel or arm.
Overall, I found this very readable, and it taught me a lot. Being unfamiliar with assembly programming in general, I had to think pretty hard about some of it to understand how it works, but that was doable and I found it rewarding. There were frequent comparisons to intel and arm, which I guess were meant to be helpful for people familiar with those architectures, but for me, just helped to understand how some of the design decisions could vary.
At this point though (2024), the book seems a bit outdated. For example, the chapter on vector instructions didn't have the detailed instruction formats because they hadn't been formalized at the time. But when I went to look them up in the current version of the spec, it seemed that the vector extension had been completely replaced. Not a big deal for me though, as I was only interested in a conceptual overview rather than the implementation specifics, but it's probably not the best place to start for the actual target audience in future.
I picked this up because I wanted to refresh myself on machine-language-level concepts, on a modern architecture, and risc-v seemed like it would be much more approachable than intel or arm.
Overall, I found this very readable, and it taught me a lot. Being unfamiliar with assembly programming in general, I had to think pretty hard about some of it to understand how it works, but that was doable and I found it rewarding. There were frequent comparisons to intel and arm, which I guess were meant to be helpful for people familiar with those architectures, but for me, just helped to understand how some of the design decisions could vary.
At this point though (2024), the book seems a bit outdated. For example, the chapter on vector instructions didn't have the detailed instruction formats because they hadn't been formalized at the time. But when I went to look them up in the current version of the spec, it seemed that the vector extension had been completely replaced. Not a big deal for me though, as I was only interested in a conceptual overview rather than the implementation specifics, but it's probably not the best place to start for the actual target audience in future.
Displaying 1 - 10 of 10 reviews