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Performance of Shared Memory in a Parallel Computer
Excerpt from Performance of Shared Memory in a Parallel Computer
The particular application that motivated this study is the performance analysis of parallel computers, especially vector machines in which processors and memories are connected by a crossbar. This means there is a communication path between each processor and memory that does not conflict with the path between any other processor and memory. However, if a memory module is addressed by more than one processor during an instruction cycle, the different accesses must be serviced sequentially, and the program cannot advance until all memory requests are satisfied. In such a case, the time to perform an instruction increases linearly with the length of the maximum request queue. Consequently, the hardware designer wishes the memory requests to be spread as uniformly as possible on average.
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Forgotten Books publishes hundreds of thousands of rare and classic books. Find more at www.forgottenbooks.com
This book is a reproduction of an important historical work. Forgotten Books uses state-of-the-art technology to digitally reconstruct the work, preserving the original format whilst repairing imperfections present in the aged copy. In rare cases, an imperfection in the original, such as a blemish or missing page, may be replicated in our edition. We do, however, repair the vast majority of imperfections successfully; any imperfections that remain are intentionally left to preserve the state of such historical works.
The particular application that motivated this study is the performance analysis of parallel computers, especially vector machines in which processors and memories are connected by a crossbar. This means there is a communication path between each processor and memory that does not conflict with the path between any other processor and memory. However, if a memory module is addressed by more than one processor during an instruction cycle, the different accesses must be serviced sequentially, and the program cannot advance until all memory requests are satisfied. In such a case, the time to perform an instruction increases linearly with the length of the maximum request queue. Consequently, the hardware designer wishes the memory requests to be spread as uniformly as possible on average.
About the Publisher
Forgotten Books publishes hundreds of thousands of rare and classic books. Find more at www.forgottenbooks.com
This book is a reproduction of an important historical work. Forgotten Books uses state-of-the-art technology to digitally reconstruct the work, preserving the original format whilst repairing imperfections present in the aged copy. In rare cases, an imperfection in the original, such as a blemish or missing page, may be replicated in our edition. We do, however, repair the vast majority of imperfections successfully; any imperfections that remain are intentionally left to preserve the state of such historical works.
44 pages, Hardcover
Published November 24, 2017
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