A Tutorial on FPGA-Based System Design Using Verilog HDL: Intel/Altera Quartus Version: Part III: A Clock/Timer and a Simple Computer

by Ming-Bo Lin

The contents of this book are designed on the basis of the problem- based-learning (PBL) approach and follow the design -> entry (in both schematic and HDL) -> verification as well as implementation. Based on this paradigm, we develop an incremental learn-by-doing method to help the student to build a sound understanding in both the design principles and the implementations of digital systems based on FPGA devices. Features of this book include•Lab projects are exercised with schematic entry first and then Verilog HDL entry.•Both functional and timing verification are performed in each entry method to ensure the resulting design can work properly in FPGA devices.•The incremental learn-by-doing method is applied to gradually introduce new concepts and hardware resources and increase the depth of lab projects.•The paradigm, design -> entry (in both schematic and HDL) -> verification as well as implementation, is employed to familiarize the reader with the right concept and use of the HDL entry method.•Optional lab projects are provided for readers to make realistic tests on FPGA devices.•Extended lab projects to broaden the reader’s background knowledge and capability.This book can be used as the textbook for the following Digital Logic Design Practice, Introduction to FPGA-Based System Design, Introduction to Digital System Practice, and Introduction to Verilog HDL.

337 pages, Paperback

Published August 10, 2018