The semiconductor industry is now at a critical juncture partly due to the question of whether microelectronic feature sizes can continue the Moore's Law pace of performance enhancement, according to Pedram (U. of Southern California) and Rabaey (U. of California, Berkeley). In this sequel to their Low-power design methodologies (1996), they introduce issues involved in the design of low-power/power-aware designs, and specific power reduction mechanisms and techniques. Sixteen other perspectives on this "power challenge" in VLSI circuits and systems are included. Annotation (c)2003 Book News, Inc., Portland, OR