Yield Modelling and Defect Tolerance in VLSI, Papers Presented at the INT Workshop on Designing for Yield, 1-3 July 1987, Oxford

by Will Moore, Wojciech Maly, Andrzej J. Strojwas (Editor)

Papers of the International Workshop on Designing for Yield, Oxford, July 1987. Objectives include discussion of topics in VLSI and designing integrated circuits to yield targets. On yield loss mechanisms and defect tolerance, alternative prospects, catastrophic yield loss models, parametric yield l

304 pages, Hardcover

First published January 1, 1988