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Computer Architecture: A Quantitative Approach
This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today. In this edition, the authors bring their trademark method of quantitative analysis not only to high performance desktop machine design, but also to the design of embedded and server systems. They have illustrated their principles with designs from all three of these domains, including examples from consumer electronics, multimedia and web technologies, and high performance computing.
IA-64 architecture and its first implementation, the Itanium
Pipeline designs for Pentium III and Pentium IV
The cluster that runs the Google search engine
EMC storage systems and their performance
Sony Playstation 2
Infiniband, a new storage area and system area network
SunFire 6800 multiprocessor server and its processor the UltraSPARC III
Trimedia TM32 media processor and the Transmeta Crusoe processor
Examines quantitative performance analysis in the commercial server market and the embedded market, as well as the traditional desktop market.
Updates all the examples and figures with the most recent benchmarks, such as SPEC 2000.
Expands coverage of instruction sets to include descriptions of digital signal processors, media processors, and multimedia extensions to desktop processors.
Analyzes capacity, cost, and performance of disks over two decades.
Surveys the role of clusters in scientific computing and commercial computing.
Presents a survey, taxonomy, and the benchmarks of errors and failures in computer systems.
Presents detailed descriptions of the design of storage systems and of clusters.
Surveys memory hierarchies in modern microprocessors and the key parameters of modern disks.
Presents a glossary of networking terms.
David A. Patterson has been teaching computer architecture at the University of California, Berkeley, since joining the faculty in 1977, and holds the Pardee Chair of Computer Science. His teaching has been honored by the ACM and the University of California. In 2000 he won the James H. Mulligan, Jr. Education Medal from IEEE "for inspirational teaching through the development of creative curricula and teaching methodology, for important textbooks, and for effective integration of education and research missions." Patterson has also received the 1995 IEEE Technical Achievement Award for contributions to RISC and shared the 1999 IEEE Reynold B. Johnson Information Storage Award for contributions to RAID. In 2000 he shared the IEEE John von Neumann Medal with John Hennessy "for creating a revolution in computer architecture through their exploration, popularization, and commercialization of architectural innovations." Patterson is a member of the National Academy of Engineering and is a fellow of both the ACM and the IEEE. In the past, he has been chair of the CS division in the EECS department at Berkeley, the ACM SIG in computer architecture, and the Computing Research Association.
The book retains its highly rated Fallacies and Pitfalls, which share the hard-won lessons of real designers; Historical Perspectives, which provide a deeper look at computer design history; Putting it all Together, which present a design example that illustrates the principles of the chapter; Worked Examples, which challenge the reader to apply the concepts, theories and methods in smaller scale problems; and Cross-Cutting Issues, which show how the ideas covered in one chapter interact with those presented in others. In addition, a new feature, Another View, presents brief design examples in one of the three domains other than the one chosen for Putting It All Together.
The authors present a new organization of the material as well, reducing the overlap with their other text, Computer Organization and A Hardware/Software Approach 2/e, and offering more in-depth treatment of advanced topics in multithreading, instruction level parallelism, VLIW architectures, memory hierarchies, storage devices and network technologies.
Also new to this edition, is the adoption of the MIPS 64 as the instruction set architecture. In addition to several online appendixes, two new appendixes will be printed in the one contains a complete review of the basic concepts of pipelining, the other provides solutions a selection of the exercises. Both will be invaluable to the student or professional learning on her own or in the classroom.
Hennessy and Patterson continue to focus on fundamental techniques for designing real machines and for maximizing their cost/performance.
Features
IA-64 architecture and its first implementation, the Itanium
Pipeline designs for Pentium III and Pentium IV
The cluster that runs the Google search engine
EMC storage systems and their performance
Sony Playstation 2
Infiniband, a new storage area and system area network
SunFire 6800 multiprocessor server and its processor the UltraSPARC III
Trimedia TM32 media processor and the Transmeta Crusoe processor
Examines quantitative performance analysis in the commercial server market and the embedded market, as well as the traditional desktop market.
Updates all the examples and figures with the most recent benchmarks, such as SPEC 2000.
Expands coverage of instruction sets to include descriptions of digital signal processors, media processors, and multimedia extensions to desktop processors.
Analyzes capacity, cost, and performance of disks over two decades.
Surveys the role of clusters in scientific computing and commercial computing.
Presents a survey, taxonomy, and the benchmarks of errors and failures in computer systems.
Presents detailed descriptions of the design of storage systems and of clusters.
Surveys memory hierarchies in modern microprocessors and the key parameters of modern disks.
Presents a glossary of networking terms.
David A. Patterson has been teaching computer architecture at the University of California, Berkeley, since joining the faculty in 1977, and holds the Pardee Chair of Computer Science. His teaching has been honored by the ACM and the University of California. In 2000 he won the James H. Mulligan, Jr. Education Medal from IEEE "for inspirational teaching through the development of creative curricula and teaching methodology, for important textbooks, and for effective integration of education and research missions." Patterson has also received the 1995 IEEE Technical Achievement Award for contributions to RISC and shared the 1999 IEEE Reynold B. Johnson Information Storage Award for contributions to RAID. In 2000 he shared the IEEE John von Neumann Medal with John Hennessy "for creating a revolution in computer architecture through their exploration, popularization, and commercialization of architectural innovations." Patterson is a member of the National Academy of Engineering and is a fellow of both the ACM and the IEEE. In the past, he has been chair of the CS division in the EECS department at Berkeley, the ACM SIG in computer architecture, and the Computing Research Association.
At Berkeley, Patterson led the design and implementation of RISC I, like...
1136 pages, Hardcover
Published May 31, 2002
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Displaying 1 - 30 of 39 reviews
September 19, 2008
My gargantuan Second Edition of Mssrs. Patterson et Hennessy, reeking with the stench of death forever associated with CS2200 (the foulest corruption of awesome material via wretched undergraduate TA fuckups 'ere I've experienced), sits off in the corner of my room, 1100+ pages of processing, parallelizing, and pipelining. When I found problems assigned to our CS6290 (High-Performance Computer Architecture) class last week out of the Fourth Edition, and that -- of course -- the exercises had been changed across editions (even if nothing else), I was plenty pissed off. I mean, come on, one of the authors is president of Stanford (and designed MIPS); the other was president of ACM and tenured at UCB (and had his hands in SPARC). I'm by no means a starving undergraduate, but I was in no way thrilled to find myself owing P&H yet another $100. To add insult to injury, this fourth edition had regressed to paperback, and slimmed down by some 600 pages. Overcoming the urge to firebomb GTB&N, I went home to LaTeX up problems 1-11 and 1-13, and find a good Unibomber jacket.
Lo, this is one of the most inspired revisions I've ever seen -- ranking with Knuth's Third, K&R's Second, or the Second as well of Abelman and Sussman (note that Dijkstra never needed more than a first (zeroth) edition -- one merely rereads A Discipline of Programming every few years and gazes back in wonder at time wasted in foolishness). The exercises have indeed been completely redone. Yes, this is normally a cause for groans and the gnashing of teeth -- the goal of invalidating previous years' and other colleges' homeworks is met, at the cost of a revue derelictia, a comedy of errors; graduate students, their ESL skills underwhelmed only by their bewilderment when handed practical tasks, cut swaths of inconsistent, incomprehensible furrow into previously-useful exercise sets -- like the great Midwestern tornadoes, they're with us only for a moment and leave naught but chaos, confusion and strewn papers in their wake. P&H have taken time out of their busy Stanford-pimping schedules to instead lovingly parameterize their exercises, presumably in combination with generators for all things Presentation, and intend to release re-parameterized sets each year (semester?) -- in this way, we assume, the motivator for new editions and thus costs is eliminated (0). This is noble, although it immediately sets a fine challenge to the motivated student: produce fully parameterized solutions to the problems, capable of taking the definition as input and generating the correct instance of output =]. In the immortal words of Tannenbaum's Structured Computer Organization (Fourth Edition): "At the end of this chapter the motivated student ought be able to leave his home, purchase a bag of transistors, and implement the PicoJavaII. Students successfully accomplishing this task will be given extra credit (and a complete psychiatric examination)." (Then again, one of Tannenbaum's students did infamously go on to buy a bag of 386's and implement an OS).
As the adderall wears off and nitrogenated liquid waste distends my innards, I grow proportionately less interested in continuing this review. Summary: if you're going to read one advanced text on processor architecture this semester, H&P4'll cure what ails ye.
(0) This is, of course, terminally brain-damaged. You solve this by making tests count for 100% of the grade (preferably in the form of a single, cumulative final), not by propping up a textbook-publishing industry having all the appeal of highly industrialized gang rape. Is this the purchasing of textbooks, or the Eastern Front circa early '45? Did we lose a war?
Lo, this is one of the most inspired revisions I've ever seen -- ranking with Knuth's Third, K&R's Second, or the Second as well of Abelman and Sussman (note that Dijkstra never needed more than a first (zeroth) edition -- one merely rereads A Discipline of Programming every few years and gazes back in wonder at time wasted in foolishness). The exercises have indeed been completely redone. Yes, this is normally a cause for groans and the gnashing of teeth -- the goal of invalidating previous years' and other colleges' homeworks is met, at the cost of a revue derelictia, a comedy of errors; graduate students, their ESL skills underwhelmed only by their bewilderment when handed practical tasks, cut swaths of inconsistent, incomprehensible furrow into previously-useful exercise sets -- like the great Midwestern tornadoes, they're with us only for a moment and leave naught but chaos, confusion and strewn papers in their wake. P&H have taken time out of their busy Stanford-pimping schedules to instead lovingly parameterize their exercises, presumably in combination with generators for all things Presentation, and intend to release re-parameterized sets each year (semester?) -- in this way, we assume, the motivator for new editions and thus costs is eliminated (0). This is noble, although it immediately sets a fine challenge to the motivated student: produce fully parameterized solutions to the problems, capable of taking the definition as input and generating the correct instance of output =]. In the immortal words of Tannenbaum's Structured Computer Organization (Fourth Edition): "At the end of this chapter the motivated student ought be able to leave his home, purchase a bag of transistors, and implement the PicoJavaII. Students successfully accomplishing this task will be given extra credit (and a complete psychiatric examination)." (Then again, one of Tannenbaum's students did infamously go on to buy a bag of 386's and implement an OS).
As the adderall wears off and nitrogenated liquid waste distends my innards, I grow proportionately less interested in continuing this review. Summary: if you're going to read one advanced text on processor architecture this semester, H&P4'll cure what ails ye.
(0) This is, of course, terminally brain-damaged. You solve this by making tests count for 100% of the grade (preferably in the form of a single, cumulative final), not by propping up a textbook-publishing industry having all the appeal of highly industrialized gang rape. Is this the purchasing of textbooks, or the Eastern Front circa early '45? Did we lose a war?
November 4, 2019
I think it's a good read. I found it practical and easy to understand, even though I'm not a big fan of comupter books, I'm more into docmuentation and technical manuals.
April 3, 2021
Now that Moore's law is at an end, how do we make computers faster? 1: The Memory Hierarchy (caches). This works pretty well, but caches can only be so large before they get slow. 2: Instruction-Level Parallelism (instruction pipelines). This is horribly complicated, doesn't work particularly well, and is subject to side channel attacks. But it doesn't require any work on the part of developers. 3: Data-Level Parallelism (GPUs). This works great for specialized applications. 4: Thread-Level Parallelism (multi-cores). Adding cores works if you don't require a lot of cross-core communication. If you do, memory coherence will become the bottleneck. 5: Request-Level Parallelism (WSCs). The cloud works well for decorrelated workloads that can be run on multi-tenant servers. 6: Domain-Specific Architectures (TPUs). If you've got something straightforward and computationally expensive (like DNN training / inference), build your own chip.
April 13, 2015
A bit wordy, like any good american book, but what really gets me about the book is the quote on the back, which will stay with me forever.
"Do you ever have the feeling that computer architectures come and go, but CA:AQA is forever?" =)
"Do you ever have the feeling that computer architectures come and go, but CA:AQA is forever?" =)
September 19, 2008
The fourth edition is a mighty step up, although this is a classic and well worth having for its expanded historical coverage, pleasantly interwoven in the text as opposed to cold exile on the cdrom.
March 13, 2020
Changed how I live my life!
April 25, 2020
Best textbook evr
February 6, 2024
Literally the bible
May 6, 2024
caching, accelerating, parallelizing, Oh My! Pretty epic. Basically everything you need to begin learning computer architecture. I dabbled in their intro book that they recommend reading before this one, but you can get all you need by grokking appendix A, B, and C, so I suggest skipping that.
The section on instruction level parallelism was particularly pertinent for me as I was reimplementing a micro architectural attack research paper for my Advanced OS final project.
The section on instruction level parallelism was particularly pertinent for me as I was reimplementing a micro architectural attack research paper for my Advanced OS final project.
November 3, 2016
An outstanding follow-up to Computer Organization and Design, Computer Architecture: A Quantitative Approach is exactly what it says on the tin: A Quantitative Approach to Computer Architecture. Shocking, I know.
I found Chapter One to be fairly uninteresting, the description of memory models in Chapter 2 and advanced pipelining concepts in Chapter 3 (particularly the discussion of Tomasulo's Algorithm) enlightening, but Chapter 4 is where the book really heats up. It starts light with vector and SIMD approaches before discussing GPU Architecture. If you've ever been mystified by how the graphics card does its job and whether your problem maps to a GPU Compute approach, read Chapter Four of this book.
Chapter 5's discussion of Thread-Level Parallelism was interesting, but not as riveting as Chapter 4, but Chapter 6 picks up again with a discussion of Warehouse Scale Computers. I didn't know that I'd care about how WSCs work, the concerns associated with them, and, well, the sheer technological wonders that they actually are, akin to a power plant or water treatment facility! Even if you read nothing else in the book, Chapter 6 is worth a read all on its own.
In addition to Appendices A, B, and C, which are included in the hardcopy, there are also online appendices D through L. As of this writing, I'm still working through Appendix F: Interconnection Networks, because the online appendices somehow don't count as part of the book in my mind, probably because they comprise more pages among them than the whole hardcopy textbook, including the references and indices.
All in all, Computer Architecture: A Quantitative Approach is a five-star book, appropriate for anyone who wants the gritty details of how hardware does its job, provided that the prospective reader started with this book's younger sibling, Computer Organization and Design, by the same authors.
I found Chapter One to be fairly uninteresting, the description of memory models in Chapter 2 and advanced pipelining concepts in Chapter 3 (particularly the discussion of Tomasulo's Algorithm) enlightening, but Chapter 4 is where the book really heats up. It starts light with vector and SIMD approaches before discussing GPU Architecture. If you've ever been mystified by how the graphics card does its job and whether your problem maps to a GPU Compute approach, read Chapter Four of this book.
Chapter 5's discussion of Thread-Level Parallelism was interesting, but not as riveting as Chapter 4, but Chapter 6 picks up again with a discussion of Warehouse Scale Computers. I didn't know that I'd care about how WSCs work, the concerns associated with them, and, well, the sheer technological wonders that they actually are, akin to a power plant or water treatment facility! Even if you read nothing else in the book, Chapter 6 is worth a read all on its own.
In addition to Appendices A, B, and C, which are included in the hardcopy, there are also online appendices D through L. As of this writing, I'm still working through Appendix F: Interconnection Networks, because the online appendices somehow don't count as part of the book in my mind, probably because they comprise more pages among them than the whole hardcopy textbook, including the references and indices.
All in all, Computer Architecture: A Quantitative Approach is a five-star book, appropriate for anyone who wants the gritty details of how hardware does its job, provided that the prospective reader started with this book's younger sibling, Computer Organization and Design, by the same authors.
May 11, 2015
Hennessy and Patterson have a lot of great numbers and facts in the book, which help ground the theory of computer architecture in reality. There's an excellent mix of content-driven chapters and helpful appendices. The only thing holding this book back from a perfect review is the heavy and obvious bias towards their own MIPS architecture, when in the modern world greater attention to x86 would probably have been more helpful.
January 7, 2020
Definitely quantitative in its approach, which was sometimes too much for me, but definitely as advertised so I won't slight it for that. It's written in that humble sort of way with respect for the topics, and that's something I always appreciate.
I found it was the most boring book ever, but occasionally I'd learn something so good that I couldn't stop reading it.
I found it was the most boring book ever, but occasionally I'd learn something so good that I couldn't stop reading it.
October 25, 2022
Sixth edition (with appendices) is dense. Extremely difficult read but enjoyed fully. If you are fairly new to the subject, I suggest ripes visualizer as a supplement (specially the six stage pipeline). Skim the chapters multiple times before diving in
June 27, 2012
Challenging, but worth it.
May 26, 2023
A must-read for understanding how computers and performance optimizations work under the hood. I scanned through the book (didn't do all the exercises and such) but still learned a ton about the context (Moore's Law), different levels of parallelisms and the use cases and hardwares associated, as well as the future of optimizations such as domain-specific architectures. Will definitely re-read for more in-depth takeaways in the future.
January 21, 2024
I was looking for an Introduction to Computer Architecture and I chose the wrong book. This is a graduate level book that assumes an understanding of Computer Architecture already. This book has sections from well known computer architecture scientists, for instance Krste A. who is credited with RISC-V open source ISA
April 6, 2019
Awesome.
February 2, 2025
Computer Architecture: A Quantitative Approach by John L. Hennessy and David A. Patterson is an absolute masterpiece—an essential read for anyone serious about understanding modern computing systems. This book sets the gold standard for learning how processors, memory, and parallel architectures are designed, optimized, and evaluated.
Hennessy and Patterson don’t just present information; they teach you how to think like a computer architect. Their rigorous, data-driven approach, combined with real-world case studies from industry, makes this book both deeply insightful and incredibly practical. The emphasis on quantitative analysis ensures that readers develop an intuition for performance trade-offs, power efficiency, and scalability—skills critical for anyone designing the next generation of computing systems.
The writing is clear, the examples are cutting-edge, and the problem sets push you to truly engage with the material. Whether you’re a student, researcher, or professional engineer, this book will challenge you, inspire you, and make you appreciate the brilliance of modern computer architecture.
An absolute must-have for anyone in the field—Hennessy and Patterson have once again delivered a timeless classic!
Hennessy and Patterson don’t just present information; they teach you how to think like a computer architect. Their rigorous, data-driven approach, combined with real-world case studies from industry, makes this book both deeply insightful and incredibly practical. The emphasis on quantitative analysis ensures that readers develop an intuition for performance trade-offs, power efficiency, and scalability—skills critical for anyone designing the next generation of computing systems.
The writing is clear, the examples are cutting-edge, and the problem sets push you to truly engage with the material. Whether you’re a student, researcher, or professional engineer, this book will challenge you, inspire you, and make you appreciate the brilliance of modern computer architecture.
An absolute must-have for anyone in the field—Hennessy and Patterson have once again delivered a timeless classic!
January 3, 2014
I think I'm probably now in the wrong position to be reading this book, as I've already had the undergrad courses on it. This is a clear and detailed look at the whole spectrum of computer architecture. It even includes a chapter on disk storage, although event I find it very difficult to get excited about RAID and disk drives!
This is a classic textbook on the subject. There's not much more to say.
This is a classic textbook on the subject. There's not much more to say.
April 22, 2014
Definitely not easy to read.
This is a comprehensive textbook on ISA/architecture design, with very recent examples (i7, cortex-a8), and explains the problems you can see with the current hardware and how some of those get solved. There's a good chapter on GPUs, and not-that-good chapter on "warehouse-sized-computers" (e.g. a google datacenter).
It's good to do at least a cursory read, just to have an idea what happens below the compiler/compiled code/assembly.
This is a comprehensive textbook on ISA/architecture design, with very recent examples (i7, cortex-a8), and explains the problems you can see with the current hardware and how some of those get solved. There's a good chapter on GPUs, and not-that-good chapter on "warehouse-sized-computers" (e.g. a google datacenter).
It's good to do at least a cursory read, just to have an idea what happens below the compiler/compiled code/assembly.
February 23, 2022
Comp arch., is a fascinating subject; this book which borders on "graduate", covers much of what remains, from comp. design and org., in sufficient detail, to grasp, certain basics. The section on domain specific ASIC designs, is especially helpful, as we approach, the five angstroms limit. Recommended.
June 25, 2015
Arguably one of the most in depth and thoughtful books on computer architecture I have ever had the pleasure to read. A book I keep coming back too. Chapter 2 Memory Hierarchy and 6 Warehouse-Scale Computers are must reads. Highly, highly recommended.
Currently reading
December 24, 2007very interesting book. introductory materials but very helpful
August 5, 2008
Patterson teaches a graduate course at Berkeley based on this book, and the lectures are available online
November 4, 2008
Best textbook ever.
July 13, 2009
Mine also mentions David A. Patterson as author.
Want to read
January 23, 2010more adventures in computer architecture
January 26, 2010
The school I teach at, SUNY Old Westbury, assigned me this book for undergraduate Computer Architecture by mistake. This book is intended for graduate students.
February 17, 2010
Textbook used for computer architecture course
Read
February 28, 2013It is a good Book
Displaying 1 - 30 of 39 reviews