SATH: Simulated Annealing C code To FPGA Hardware compiler: Customizing Pipelined Simulated Annealing IP cores with a dedicated C to FPGA compiler

by Jonathan Phillips

A tool flow is presented for deriving accelerator circuits on an FPGA from ANSI C source code by exploring architecture solutions that conform to a preset template through scheduling and mapping algorithms. A case study carried out on simulated annealing-based scheduling software used for spacecraft systems is explained. The goal of the tool is the derivation of a design that maximizes throughput while minimizing footprint. Results obtained are compared with a peer C to RTL tool, a space-borne embedded processor and a commodity desktop processor for a variety of problems.

132 pages, Paperback

Published July 8, 2009

About the author

Dr. Jonathan Phillips is Professor of Crusading History in the Department of History, Royal Holloway, University of London, UK. His scholarly contributions to the crusades include the books Defenders of the Holy Land: Relations Between the Latin East and West, 1119-1187, The Crusades, 1095-1197, and most recently, The Fourth Crusade and the Sack of Constantinople. His articles have appeared in a number of British publications including BBC History, History Today, and the Independent. Additionally, he is regularly consulted on radio and television programs as a leading expert on crusades history.