Dayton Outar’s Reviews > Digital Fundamentals > Status Update

Skipped through to Chapter 12, "Signal Conversion and Processing" on page 697.

I remember doing exercises up to Chapter 12 in university.

Now at 6–1 "Half and Full Adders". Page 314.

Now at 5–6 "Combinational Logic with VHDL". Page 283.

At section 5-5, page 280 after speeding through chapters 1 and 4. I'm familiar with the content. Just need to review the following sections,
- 1-7
- 1-8
- 2-12
- 3-7
- 3-8
- 3-9